Question 1

What is stored in PTR (page table register)?

It stores the address to the page table that is specific to the currently executed program.

Question 2

What is the difference between TLB and page table?

There are 5 columns in Page table, namely, the index(VPN), V, D, R, and the data (PPN). However, there are 6 columns in a TLB that are identical to the 5 columns in Page table except for the Tag column. In particular, the index now stores the order in which the entry is added in TLB and the VPN is stored instead in the Tag.

Question 3

What will happen when all entries in a TLB have both of valid bit and reference bit set to 1 before a new translation is added?

Kick out the first entry and store that instead.

Question 4

What should we take care of before a page swap?

Before a page swap, if the dirty bit of this page is 1 in the page table, then search the entire cache such that whenever there is a dirty bit of the cache entry that belongs to this page is 1, write the data of that entry back to this page in RAM, and eventually, write it back to disk.

Question 5

What are the two interpretations of physical addresses in terms of going to RAM or going to cache?

The interpretation related to RAM is as follows: interpret the first 20 bits as a physical page number, and the later 12 bits as an offset. We combine them together as an RAM index. The interpretation related to cache is as follows: we have no luxury to keep the last two bits, since they are always two zeros. We interpret the 5 bits to the left of the two useless bits as the cache index. Then, interpret the left 25 bits as the cache tag.

Question 6

Why does offset have 12 bits?

Since the page size is 4KB. $2^{12} = 4 * 2^{10} = 4096‚Äč$