Multi-cycle processor


Key features of multicycle processor implementations include:

  1. instead of using 1 cycle to execute 1 instruction, use several clock cycles,

  2. thus, the original long clock cycle is broken up into a shorter clock cycle,

  3. at the end of each clock cycle, all data used in subsequent cycles must be stored in a state element, i.e., the intermediate register,

  4. an instruction has exclusive use of the datapath until it completes, and

  5. the transition from one stage in single-cycle to five stages in multicycle.

Intermediate registers for five stages


  • This is the basic single cycle datapath with added intermediate registers.
  • These intermediate register files store information computed in one stage that is needed for the subsequent states.

Multicycle control


  • All instructions are given 5 steps / stages to complete, even if some may not need all.
  • CONTROL ensures that every step occurs in order and intermediate registers are only updated when used.

Stage #1 - Instruction Fetch


  • instruction is fetched from instruction memory
  • the value of PC plus 4 and other appropriate data will be written to IF/ID intermediate register at end of this clock cycle, controlled by the multi-cycle controller
  • in particular, control bits are all 1 for the current immediate register being written to, and 0 for others.

Control bits are presumably referring to RegWrite bits, since registers only have one control bit.

Stage #2 - Instruction Decode


  • same as above, all the other intermediate registers have control bits set to 0 and the active register, i.e., ID/EX register, is set to 1
  • perform read from register files, including reading from IF/ID and the main register file

The first two steps are common to all instructions. By the third clock cycle, datapath knows which instruction is in the datapath.

Stage #3 - Instruction Execute


  • If it is a branch instruction, the adder will be ready for the target address. The ALU is responsible for determining whether the jump action is going to be taken or not.

Stage #4 - Memory


  • PC will possibly be updated at this stage.

Stage #5 - Write Back



  • Recall that single-cycle computer has 600ps clock cycle.
  • Each multicycle clock must be speed of slowest component, i.e. memory access costs 200ps.
  • Each instruction has to take 5 clock-cycles even though some may not need all.
  • The time per instruction is 1000ps.
  • Note that this is much slower than single cycle and at any time about 80% of hardware is unused.
  • PC may be updated more than once. PC gets updated at the first stage and possibly updated again in MEM stage.
  • Notice that there is no need for an intermediate register for the fifth stage.